1. Field of the Invention
The present invention relates to a memory circuit, such as a dynamic RAM (DRAM), and more particularly to a memory circuit with a faster reset operation of bit lines.
2. Description of the Related Art
An increase of capacity and speed is demanded for memory devices, such as DRAM. For example, page mode and burst mode have been proposed for increasing speed. Also recently, it is proposed to decrease the random access cycle itself, which involves changing not only column addresses but also row addresses. An example is a fast cycle RAM (FCRAM, trademark of Fujitsu, Ltd.), which has a shorter cycle time of random access operation, proposed in the Nikkei Electronics, Jun. 15, 1998 issue, pages 163-171, and in the 1998 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pages 22-25.
FIG. 1 is a diagram depicting a circuit example of a conventional memory device. In the memory device in FIG. 1, a sense amplifier SA, a bit line clamper and short circuit BLR, and a column gate CLG are disposed between a first bit line pair BL0 and /BL0 and a second bit line pair BL1 and /BL1, which are disposed in the lateral column direction. The sense amplifier SA, the bit line clamper and short circuit BLR and the column gate CLG are shared by the first and the second bit line pairs BL0 and /BL0 and BL1 and /BL1, and are connected to the first bit line pair or the second bit line pair by conducting one of the first and second bit line transfer gates BLT0 and BLT1 disposed there between.
At a first and second cell matrices CM0 and CM1 disposed at the left and right, word lines WL0 and WL1 are disposed, and memory cells MC0 and MC1 are disposed at the cross-positions of the word lines and the bit lines. And a plurality of the circuits shown in FIG. 1 are disposed as columns in the word line direction.
The sense amplifier SA in FIG. 1 comprises N channel transistors N1, N2 and N3 and P channel transistors P1, P2 and P3, and is activated when the transistor N1 conducts responding to a sense amplifier activation signal lez at the N side, pulls down a node nsa to the ground voltage Vss, and the transistor P1 conducts responding to a sense amplifier activation signal lex at the P side, and pulls up a node psa to the internal power supply Vii. By activation of the sense amplifier, the bit line pairs are driven and amplified to the ground voltage Vss and the internal power supply Vii.
The bit line transfer gates BLT0 and BLT1 comprise N channel transisters N10 and N11 and N12 and N13 respectively, and connect the corresponding bit line pair to the sense amplifier SA and the bit line clamper and the short circuit BLR under control of respective transfer control signals Blt0 or Blt1.
In the bit line clamper and short circuit BLR, the N channel transistors N4, N5 and N6 conduct responding to a bit line reset signal bre, and the transistor N4 shorts the bit line pairs, and at the same time, the transistors N5 and N6 clamp the bit line pairs to the precharge level Vii/2, which is 1/2 of the internal power supply Vii. The column gate CLG comprises N channel transistors N14 and N15, which connect the bit line pairs to the data bus line pair DB and /DB responding to a column select signal c1.
According to the operation of the above mentioned conventional memory device, both of the bit line transfer gates BLT0 and BLT1 conduct in reset status, the transistors N4-N6 of the bit line clamper and short circuit BLR conduct by the bit line reset signal bre, which shorts both of the bit line pairs and sets the bit line pairs to the bit line precharge level Vii/2. If the memory cell MC0 is selected here, the bit line transfer gate BLT1 side no longer conducts, the bit line clamper and short circuit BRL is reset so that the transistors N4, N5, N6 are non-conductive, the word line WL0 is driven, and a very small voltage difference is generated between the first bit line pair BL0 and /BL0 according to the charge stored in the memory cell MC0. Then the sense amplifier activation signal lez rises and lex falls, which activates the sense amplifier SA, amplifies the very small voltage difference generated between the bit line pair BL0 and /BL0, and as a result one bit line is driven to the internal power supply Vii and the other bit line is driven to the ground voltage Vss. The bit line pair BL0 and /BL0 is connected to the data bus line pair DB and /DB responding to the column select signal c1, and a read signal is output via a read amplifier and an output circuit, which are not illustrated. When the word line WL0 falls and the memory cell MC0 is written again, the sense amplifier SA is deactivated, and at the same time, the bit line transfer gate BLT1 side becomes conductive again, and the transistors of the bit line clamper and short circuit BLR conduct responding to the bit line reset signal bre, and short and clamp the bit line pairs BL0 and /BL0 and BL1 and /BL1 to the precharge level Vii/2.
In the configuration of the memory device shown in FIG. 1, the left and right bit line pairs share one sense amplifier SA, and the bit line transfer gates BLT0 and BLT1 connect one bit line pair to the sense amplifier SA. Also, the bit line clamper and short circuit BLR, which is a circuit for resetting the bit line, is disposed next to the sense amplifier SA, and is also shared by the left and right bit line pairs. As a consequence, this configuration is effective in terms of layout efficiency when relatively long bit line pairs are connected to one sense amplifier and when the number of rows of sense amplifier SA of the memory device is small. Because a pair of memory cell arrays CM0, CM1 can share the sense amplifier row.
However, the bit line clamper and short circuit BLR is connected to the bit line pairs by way of the bit line transfer gates BLT0 and BLT1, therefore the on-resistance of the transistors N10-N13 of the bit line transfer gates makes the time for the reset operation of the bit line pairs long. Such a lengthy reset operation time makes the cycle time of the random access operation longer.
FIG. 2 is a diagram depicting another circuit example of a conventional memory device. The same numerals as in FIG. 1 are used in FIG. 2 if the parts are the same. In the example of prior art in FIG. 2, the left and right bit line pairs BL0 and /BL0 and BL1 and /BL1 disposed in the column direction, share the sense amplifier SA, just like the first example of prior art. Therefore, the bit line transfer gates BLT0 and BLT1 are disposed between the sense amplifier SA and each bit line pair respectively. As with the sense amplifier SA, the column gate CLG is also shared by both bit line pairs.
In the example of prior art shown in FIG. 2, the bit line clamper and short circuit BLR, which is a bit line reset circuit, is disposed for each bit line pair in order to increase the speed of operation to short and reset the bit line pairs to the precharge level Vii/2. In other words, the bit line clamper and short circuit BLR0 is connected to the right bit line pair BL0 and /BL0, shorts the connected bit line pair BL0 and /BL0 responding to the reset signal blt1, and clamps the bit line pair to the precharge level Vii/2. In the same way, the bit line clamper and short circuit BLR1 is connected to the left bit line pair BL1 and /BL1, shorts the connected bit line pair BL1 and /BL1 responding to the reset signal blt0, and clamps the bit line pair to the precharge level Vii/2. The respective bit line clamper and short circuit BLR0, BLR1 comprises N channel transistors for shorting N4 and N24, and N channel transistors for clamping N5 and N6, and N25 and N26 in the same way.
In the case of the example of prior art shown in FIG. 2, the same control signal blt1 controls the right bit line clamper and short circuit BLR0 and the left bit line transfer gate BLT1, and the same control signal blt0 controls the left bit line clamper and short circuit BLR1 and the right bit line transfer gate BLT0. As a consequence, the bit line clamper and short circuits BLR0 and BLR1 can directly short and clamp the respective bit line pair to the precharge level without passing through the bit line transfer gate. As a result, the reset operation time can be shorter than the example of prior art in FIG. 1.
However, the clamper circuits comprised of the transistors N5 and N6, and N25 and N26 of the above mentioned bit line clamper and short circuits BLR0, BLR1 are required, only when for example the non-selected bit lines are maintained to the precharge level (internal power supply Vii) for a long time, and the precharge level drops due to the junction leakage in the substrate of the memory device so that the short operation alone between the bit line pairs at reset cannot set the bit line pairs to the precharge level Vii/2, which is 1/2 of the internal power supply. Therefore, the short circuit mainly resets the bit line pairs, and the operation of the bit line clamper circuits does not influence the reset operation of the bit line pairs very much.
In the example of prior art shown in FIG. 2, on the other hand, the circuit BLR0 or BRL1, comprised of the bit line clamper circuit and the short circuit for resetting the bit lines, is disposed for each bit line pair. Therefore, in the case of a memory device where the speed of the reset operation of the bit line pairs is increased by decreasing the length of the bit line pairs, disposing a clamper circuit for each bit line pair has a negative effect on increasing integration. In other words, if the clamper circuit, which does not contribute to increasing the speed of the reset operation of bit line pairs very much, is disposed for each bit line pair, it does not contribute to increasing the speed of the reset operation, but rather decreases area efficiency.
Especially in the case of the above mentioned FCRAM which has a shorter cycle time of random access, the length of the bit line pairs is shortened by subdivision to decrease the drive operation time for the bit line pairs by the sense amplifier SA and to decrease the reset operation time of the bit line pairs. Because of this, the number of sense amplifier rows and the number of bit line pairs to share the sense amplifiers increase in the memory device as a whole. As a consequence, in the architecture of FCRAM, disposing a clamper circuit for each bit line pair, as seen in FIG. 2, drops area efficiency. Also sharing the bit line pair short circuit by the bit line pairs, as shown in FIG. 1, is a configuration which makes it difficult to decrease the reset time of the bit line pairs, as mentioned above.
Also in the case of FCRAM, decreasing the cycle time results in a more frequent reset operation, which increases power consumption. Therefore, power saving of the bit line clamper circuit and the short circuit for resetting bit lines is also demanded.